1. Field of the Invention
The present invention generally relates to electronic memories and, more particularly, to enhancing performance and testability of electronic memories used in data processing equipment.
2. Description of the Prior Art
The operation of many microprocessor controlled devices and data processors in general relies, at a most basic level, relies on the ability of the processor to retrieve data or instructions from memory, perform an operation on such data or in accordance with such instruction and to store a resulting digital signal in memory, a register or other digital signal storage structure with an extremely high degree of reliability. For this reason, many error checking architectures and techniques have been developed and incorporated into processors or associated hardware or software in order to increase the reliability with which the processor functions. It is equally important that the storage structure respond reliably and unambiguously when digital signals are applied to it and various testing procedures have been developed to ensure reliable operation thereof, particularly in combination with data processors.
Some high performance processor architectures have adopted multiple-port storage structures in order to enhance performance of certain operations. A look-aside buffer used in some cache applications is a familiar example of an application where multiple memory input ports provides a performance enhancement. In such multiple-port storage devices, simultaneous write operations which could involve attempts to store inconsistent digital signals are not allowed. However, for purposes of testing of the multiple-port storage devices one recent and rigorous testing procedure requires that an unambiguous signal storage state must be achieved even when simultaneous write operations are attempted at different ports.
The reason for such a test criteria is that stored data must not be corrupted by the possibility of an ambiguous response if simultaneous write operations were to occur. That is, one set of digital data signals applied to the storage device must be correctly stored to avoid errors which are not recoverable. If a different set of digital data signals must be stored in a subsequent processor cycle to correctly accomplish an operation, such storage can be readily accomplished while corrupted data signals may cause other errors to be propagated through the system.
In the past, it has been the conventional practice to provide logic circuitry between inputs at various ports of a multiple-port storage device to provide a priority between input ports. Such logic circuitry, at a minimum, determines the simultaneous presence of a signal at two or more ports to generate appropriate enable signals in order to prevent simultaneous application of the signals to a memory cell. This selective port enablement function is conventionally accomplished using a comparator. However, regardless of the nature of the circuit, logic signals must be propagated through it before a write operation can be attempted, resulting in reduced speed of operation. Further, comparators must generally be merged with write decoders which complicates circuit design and fabrication and may further slow the performance of all write operations. Such reduced speed of performance is particularly undesirable where the memory or storage device is arranged to perform plural memory operations in a single cycle, such as in a so-called write-before-read mode of operation. These problems are aggravated by increases in logic circuit or comparator complexity as the number of ports is increased.